Pipelined processors typically include a store queue (or store buffer) for buffering store memory operations (referred to herein also as “stores”) prior to the store memory operations being completed (e.g., committed to a data cache or memory). The buffering of store memory operations in a store queue permits a processor to execute additional instructions without having to wait for actual completion of prior stores. Accordingly, when a load memory operation (referred to herein also as a “load”) executes, a determination is made of whether a data hazard exists between the load memory operation and any store memory operations buffered in the store queue. A data hazard between a load and store can exist, for example, when a load requires data from the same line address and bytes (of a cache) to which a buffered store has yet to write.
One conventional technique for handling a data hazard is described in U.S. Pat. No. 6,393,536, entitled “Load/Store Unit Employing Last-In-Buffer Indication For Rapid Load-Hit-Store”. The technique includes maintaining a “forwarding” buffer that is separate from the store queue, which forwarding buffer keeps track of prior loads and stores. Each store in the forwarding buffer includes a last-in-buffer (LIB) indicator that indicates whether the store is the youngest store (i.e., the store nearest a given load in program order and, therefore, the store which contains the data that the load should receive) and only allows the data corresponding to the youngest store to be forwarded to the load. Because the data in the forwarding buffer remains until the data is removed, the forwarding buffer behaves as a small cache, and as such, additional controls are required to manage the data contained within the forwarding buffer. For example, when data is cast from the main data cache, corresponding data must also be invalidated from the forwarding buffer. In addition, extra area is required in a processor architecture to support a store queue along with a separate forwarding buffer.